With the rapid development of processor techniques, an existing memory system is insufficient to match a processor system that has undergone rapid development, which causes an increasingly severe development bottleneck for memory techniques. The development bottleneck for memory techniques is mainly reflected in two aspects that include a low effective utilization rate of a memory bandwidth and high power consumption of a memory system.
In a related art, to lower power consumption of a memory system, an organization manner of a memory chip is changed to improve a processing manner of a memory access request. One memory access request is processed by one subarray in one memory chip, instead of being evenly distributed to all memory chips or all subarrays of one memory chip, so that when a memory access request is processed, only a memory chip relevant to the memory access request is activated while other subarrays that are not activated are in a low power consumption mode.
In the forgoing implementation process for processing the memory access, a longer time is needed to transmit data when one memory access request is processed by one subarray in one memory chip and a memory controller can send a next memory access request to the memory chip only after receiving response information returned from the memory chip. This results in a relatively long time delay in processing a memory access request.